Best Power B510-2000P Spécifications

CC1100ESWRS082Page1of92Low-PowerSub-GHzRF Transceiver(470-510 MHz & 950-960 MHz)ApplicationsUltra low-power wireless applicationsoperating in the

CC1100ESWRS082Page10of924.2RF Receive SectionTA= 25C, VDD = 3.0V if nothing else stated. All measurement results are obtained using theCC1100EEMrefer

CC1100ESWRS082Page11of92TA= 25C, VDD = 3.0V if nothing else stated.All measurement results are obtained using theCC1100EEMreference designs([3]and[4]

CC1100ESWRS082Page12of92Table7: Typical Variation in Sensitivityover Temperature andSupply Voltage,955MHz,76.8kBaudGFSK, Sensitivity Optimized Setting

CC1100ESWRS082Page13of924.3RF Transmit SectionTA= 25C, VDD = 3.0V, +10dBm if nothing else stated. All measurement results are obtained using theCC110

CC1100ESWRS082Page14of92Table9: Typical Variation in Output Power over Temperature and Supply Voltage,480MHz,+10 dBmOutputPower SettingTable10: Typica

CC1100ESWRS082Page15of924.6Frequency Synthesizer CharacteristicsTA= 25C,VDD = 3.0 V if nothing else is stated.All measurement results are obtained us

CC1100ESWRS082Page16of924.8DC CharacteristicsTA= 25C if nothing else stated.Table15: DC Characteristics4.9Power-On ResetWhen the power supply complie

CC1100ESWRS082Page17of92Pin #Pin NamePin typeDescription1SCLKDigital InputSerial configuration interface, clock input2SO (GDO1)Digital OutputSerial co

CC1100ESWRS082Page18of926Circuit DescriptionBIASPARBIASXOSC_Q1XOSC_Q2CSnSISO (GDO1)XOSCSCLKLNA090FREQSYNTHADCADCDEMODULATORFEC / INTERLEAVERPACKET HAN

CC1100ESWRS082Page19of92signals are joined together (C131, C121, L121and L131for the470MHzreferencedesign[3],andL121, L131, C121, L122, C131, C122and

CC1100ESWRS082Page2of92Key FeaturesRF PerformanceHigh sensitivity(–112dBmat 1.2kBaud,480MHz, 1% packet error rate)Low current consumption(15.5mA inR

CC1100ESWRS082Page20of927.7Antenna ConsiderationsThe reference designs([3]and0)contain anSMA connector and are matched for a 50load.The SMA connector

CC1100ESWRS082Page21of92Antenna(50Ohm)DigitalInteface1.8V-3.6V power supply6GDO07CSn8XOSC_Q19AVDD10XOSC_Q2SI20GND19DGUARD18RBIAS17GND161SCLK2SO(GDO1)3

CC1100ESWRS082Page22of92Table19:Bill Of Materials for the Application Circuit7.8PCB Layout RecommendationsThe top layer should be used for signalrouti

CC1100ESWRS082Page23of92100%.SeeFigure8for top solder resist andtop paste masks.Eachdecoupling capacitor should be placedas close as possible to the s

CC1100ESWRS082Page24of92Transmit modeReceive modeIDLEManual freq.synth.calibrationRX FIFOoverflowTX FIFOunderflowFrequencysynthesizer onSFSTXONSRX or

CC1100ESWRS082Page25of929Configuration SoftwareTheCC1100Ecanbeconfiguredusing theSmartRFStudio software[8]. The SmartRFStudio software is highly rec

CC1100ESWRS082Page26of920A5A4A3A2A0A1DW71Read from register:Write to register:Hi-ZXSCLK:CSn:SISOSISOHi-ZtsptchtcltsdthdtnsXXHi-ZXHi-ZS7XDW6DW5DW4DW3DW

CC1100ESWRS082Page27of9210.1Chip Status ByteWhen the header byte, data byte,or commandstrobeis sent on the SPI interface, the chipstatus byte is sent

CC1100ESWRS082Page28of92burst bit(B)in the headerbyte. The addressbits (A5–A0)setthe start address in aninternal address counter. This counter isincre

CC1100ESWRS082Page29of92expectsa header bytewiththeburst bit set tozero and one data byte. After the data byte,anewheader byteis expected; hence, CSn

CC1100ESWRS082Page3of92AbbreviationsAbbreviations used in thisdata sheet are described below.ACPAdjacent Channel PowerMSKMinimum Shift KeyingADCAnalog

CC1100ESWRS082Page30of9211Microcontroller Interface and Pin ConfigurationIn a typical system,theCC1100Ewill interface toa microcontroller. This microc

CC1100ESWRS082Page31of9212Data Rate ProgrammingThe data rate used when transmitting, or thedata rate expected in receive is programmedby theMDMCFG3.DR

CC1100ESWRS082Page32of9214Demodulator, Symbol Synchronizer,and Data DecisionTheCC1100Econtains an advanced and highlyconfigurable demodulator. Channel

CC1100ESWRS082Page33of9215Packet Handling Hardware SupportTheCC1100Ehas built-in hardware support forpacket orientedradio protocols.In transmit mode,

CC1100ESWRS082Page34of92Figure14: Data Whitening in TX Mode15.2PacketFormatThe format of the data packet can beconfiguredand consists of the following

CC1100ESWRS082Page35of92packets, infinite packet length mode must beused.Fixed packet length mode is selected bysettingPKTCTRL0.LENGTH_CONFIG=0. Thede

CC1100ESWRS082Page36of920,1,...,88,...255,0,...,88,...,255,0,...,88,...,255,0,...

CC1100ESWRS082Page37of92The modulator will first send the programmednumber of preamble bytes. If data is availablein the TX FIFO, the modulator will s

CC1100ESWRS082Page38of92It is recommended to employ an interruptdriven solutionsincehigh rate SPI pollingreducesthe RX sensitivity. Furthermore, asexp

CC1100ESWRS082Page39of9216.3Amplitude ModulationTheCC1100Esupports two different forms ofamplitude modulation: On-Off Keying (OOK)and Amplitude Shift

CC1100ESWRS082Page4of92Tableof ContentsAPPLICATIONS...

CC1100ESWRS082Page40of9217.3RSSIThe RSSI value is an estimate of the signalpowerlevel in the chosenchannel. This valueis based on the current gain set

CC1100ESWRS082Page41of92-120-110-100-90-80-70-60-50-40-30-20-100-120-110-100-90-80-70-60-50-40-30-20-100Input Power (dBm)RSSI Readout (dBm)1.2 kBaud38

CC1100ESWRS082Page42of92level and is thus useful to detect signals inenvironments with time varying noise floor.See more in Section17.4.2.Carriersense

CC1100ESWRS082Page43of9217.5Clear Channel Assessment (CCA)The Clear Channel Assessment(CCA)is usedto indicate if the current channel is free orbusy. T

CC1100ESWRS082Page44of9218.2InterleavingDatareceived through radio channels willoften experience burst errors due tointerference and time-varying sign

CC1100ESWRS082Page45of9219Radio ControlTX19,20RX13,14,15IDLE1CALIBRATE8MANCAL3,4,5SETTLING9,10,11RX_OVERFLOW17TX_UNDERFLOW22RXTX_SETTLING21FSTXON18SFS

CC1100ESWRS082Page46of92signal with a frequency ofCLK_XOSC/192.However, to optimize performance in TX andRX,an alternative GDO setting from thesetting

CC1100ESWRS082Page47of9219.3Voltage Regulator ControlThe voltage regulator to the digital core iscontrolled by the radio controller. When thechip ente

CC1100ESWRS082Page48of9219.5WakeOn Radio (WOR)The optional Wake on Radio (WOR)functionality enablestheCC1100Eto periodicallywake up fromSLEEPand liste

CC1100ESWRS082Page49of92RC oscillator calibration is turned off,it willhave to be manually turned on again ifthetemperatureand/orthesupply voltagechan

CC1100ESWRS082Page5of9214DEMODULATOR, SYMBOLSYNCHRONIZER, AND DATA DECISION...3214.1FREQUENCYOFFSETCOMPENSATION...

CC1100ESWRS082Page50of9220Data FIFOTheCC1100Econtains two 64 byte FIFOs, onefor received data and one for data to betransmitted. The SPI interface is

CC1100ESWRS082Page51of9256 bytes8 bytesOverflowmarginUnderflowmarginFIFO_THR=13FIFO_THR=13RXFIFOTXFIFOFigure24Example of FIFOs at Threshold53545556535

CC1100ESWRS082Page52of9222VCOThe VCO is completely integrated on-chip.22.1VCO and PLL Self-CalibrationThe VCO characteristics vary with temperatureand

CC1100ESWRS082Page53of92If OOK modulation is used, the logic 0 andlogic 1 power levels shallbe programmed toindex 0 and 1 respectively.Table 33contain

CC1100ESWRS082Page54of92configuration of thePATABLE.Figure27shows some examples of ASK shaping.e.g 6PA_POWER[2:0]in FREND0 registerPATABLE(0)[7:0]PATA

CC1100ESWRS082Page55of92GDOx_CFG[5:0]Description0 (0x00)Associated to the RX FIFO: Asserts when RX FIFO is filled at or above the RX FIFO threshold. D

CC1100ESWRS082Page56of9227Asynchronous and Synchronous Serial OperationSeveral features and modes of operation havebeen included in theCC1100Eto provi

CC1100ESWRS082Page57of9228System Considerationsand Guidelines28.1SRD RegulationsInternational regulations and national lawsregulate the use of radio r

CC1100ESWRS082Page58of92TheCC1100Eis highly suited for FHSS or multi-channel systems due to its agile frequencysynthesizer and effective communication

CC1100ESWRS082Page59of9228.5Low Cost SystemsAs theCC1100Eprovides1.2-500kBaudmulti-channel performance without any externalSAW or loopfilters, a veryl

CC1100ESWRS082Page6of9229.3STATUSREGISTERDETAILS...

CC1100ESWRS082Page60of92Table41summarizes the SPI address space.The address to use is given by adding thebase address to the left and the burst andrea

CC1100ESWRS082Page61of92AddressRegisterDescriptionPreserved inSLEEP StateDetails onPage Number0x00IOCFG2GDO2output pin configurationYes640x01IOCFG1GDO

CC1100ESWRS082Page62of92AddressRegisterDescriptionDetails on page number0x30 (0xF0)PARTNUMPart number fortheCC1100E850x31 (0xF1)VERSIONCurrent version

CC1100ESWRS082Page63of92WriteReadSingle ByteBurstSingle ByteBurst+0x00+0x40+0x80+0xC00x00IOCFG20x01IOCFG10x02IOCFG00x03FIFOTHR0x04SYNC10x05SYNC00x06PK

CC1100ESWRS082Page64of9229.1Configuration Register Details–Registers with preserved values inSLEEPstate0x00: IOCFG2–GDO2Output Pin ConfigurationBitFie

CC1100ESWRS082Page65of920x03: FIFOTHR–RX FIFO and TX FIFO ThresholdsBitField NameResetR/WDescription70R/WReserved, write 0 for compatibility with poss

CC1100ESWRS082Page66of920x04: SYNC1–Sync Word, High ByteBitField NameResetR/WDescription7:0SYNC[15:8]211 (0xD3)R/W8 MSB of 16-bit sync word0x05: SYNC0

CC1100ESWRS082Page67of920x08: PKTCTRL0–Packet Automation ControlBitField NameResetR/WDescription7R0Not used6WHITE_DATA1R/WTurn data whitening on / off

CC1100ESWRS082Page68of920x0B: FSCTRL1–Frequency Synthesizer ControlBitFieldNameResetR/WDescription7:6R0Not used50R/WReserved4:0FREQ_IF[4:0]15(0x0F)R/W

CC1100ESWRS082Page69of920x10: MDMCFG4–Modem ConfigurationBitField NameResetR/WDescription7:6CHANBW_E[1:0]2 (0x02)R/W5:4CHANBW_M[1:0]0 (0x00)R/WSets th

CC1100ESWRS082Page7of921Absolute Maximum RatingsUnder no circumstances must the absolute maximum ratings giveninTable1be violated. Stressexceeding one

CC1100ESWRS082Page70of920x12: MDMCFG2–Modem ConfigurationBitField NameResetR/WDescription7DEM_DCFILT_OFF0R/WDisable digital DC blocking filter before

CC1100ESWRS082Page71of920x13: MDMCFG1–Modem ConfigurationBitField NameResetR/WDescription7FEC_EN0R/WEnable Forward Error Correction (FEC) with interle

CC1100ESWRS082Page72of920x15: DEVIATN–Modem Deviation SettingBitField NameResetR/WDescription7R0Not used.6:4DEVIATION_E[2:0]4(100)R/WDeviation exponen

CC1100ESWRS082Page73of920x16: MCSM2–Main Radio Control StateMachine ConfigurationBitField NameResetR/WDescription7:5R0Not used4RX_TIME_RSSI0R/WDirect

CC1100ESWRS082Page74of920x17: MCSM1–Main Radio Control State Machine ConfigurationBitField NameResetR/WDescription7:6R0Not used5:4CCA_MODE[1:0]3 (11)R

CC1100ESWRS082Page75of920x18: MCSM0–Main Radio Control StateMachine ConfigurationBitField NameResetR/WDescription7:6R0Not used5:4FS_AUTOCAL[1:0]0 (00)

CC1100ESWRS082Page76of920x19: FOCCFG–Frequency Offset Compensation ConfigurationBitField NameResetR/WDescription7:6R0Not used5FOC_BS_CS_GATE1R/WIf set

CC1100ESWRS082Page77of920x1A: BSCFG–Bit Synchronization ConfigurationBitField NameResetR/WDescription7:6BS_PRE_KI[1:0]1 (01)R/WThe clock recovery feed

CC1100ESWRS082Page78of920x1B: AGCCTRL2–AGCControlBitField NameResetR/WDescription7:6MAX_DVGA_GAIN[1:0]0 (00)R/WReduces the maximum allowable DVGA gain

CC1100ESWRS082Page79of920x1C: AGCCTRL1–AGC ControlBitField NameResetR/WDescription7R0Not used6AGC_LNA_PRIORITY1R/WSelects between two different strate

CC1100ESWRS082Page8of924Electrical Specifications4.1Current ConsumptionTA= 25C, VDD = 3.0V if nothing else stated.All measurementresults are obtained

CC1100ESWRS082Page80of920x1D: AGCCTRL0–AGC ControlBitField NameResetR/WDescription7:6HYST_LEVEL[1:0]2 (10)R/WSets the level of hysteresis on the magni

CC1100ESWRS082Page81of920x1F: WOREVT0–Low Byte Event0 TimeoutBitField NameResetR/WDescription7:0EVENT0[7:0]107 (0x6B)R/WLow byte ofEVENT0timeout regis

CC1100ESWRS082Page82of920x21: FREND1–Front End RX ConfigurationBitField NameResetR/WDescription7:6LNA_CURRENT[1:0]1 (01)R/WAdjusts front-end LNA PTAT

CC1100ESWRS082Page83of920x24: FSCAL2–Frequency Synthesizer CalibrationBitField NameResetR/WDescription7:6R0Not used5VCO_CORE_H_EN0R/WChoose high (1)/l

CC1100ESWRS082Page84of9229.2Configuration Register Details–Registers that LooseProgramming inSLEEP State0x29: FSTEST–Frequency Synthesizer Calibration

CC1100ESWRS082Page85of920x2E: TEST0–Various TestSettingsBitField NameResetR/WDescription7:2TEST0[7:2]2 (0x02)R/WThe value to use in this register is g

CC1100ESWRS082Page86of920x35 (0xF5): MARCSTATE–Main Radio Control State Machine StateBitField NameResetR/WDescription7:5R0Not used4:0MARC_STATE[4:0]RM

CC1100ESWRS082Page87of920x38 (0xF8): PKTSTATUS–Current GDOx Status and PacketStatusBitField NameResetR/WDescription7CRC_OKRThe last CRC comparison mat

CC1100ESWRS082Page88of920x3D (0xFD): RCCTRL0_STATUS–Last RC Oscillator Calibration ResultBitField NameResetR/WDescription7R0Not used6:0RCCTRL0_STATUS[

CC1100ESWRS082Page89of9230Package Description (QFN20)30.1Recommended PCBLayout for Package (QFN20)Figure29: Recommended PCBLayout forQFN20 Package30.2

CC1100ESWRS082Page9of92Table4: Electrical SpecificationsTable5: Typical Variation in TX Current Consumption overTemperature and Supply Voltage,955MHz

CC1100ESWRS082Page90of9230.3Ordering InformationOrderableDeviceStatus(1)PackageTypePackageDrawingPinsPackageQtyEco Plan(2)LeadFinishMSL PeakTemp(3)CC1

CC1100ESWRS082Page91of92References[1]CC1101 Datasheet[2]CC1100 Datasheet[3]CC1100EEM470MHz Reference Design[4]CC1100EEM950MHz Reference Design[5]CC110

CC1100ESWRS082Page92of9231General Information31.1Document HistoryRevisionDateDescription/ChangesSWRS082April 2009Firstdatasheet releaseTable43: Docume

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